1. Field of the Invention
This invention relates to a partially relaxable dielectric structure and its application. More particularly, this invention relates to a novel integrated circuit memory structure and the method for making an integrated circuit memory.
2. Description of the Prior Art
Integrated circuit memory devices are known in the prior art. FIG. 1a shows a cross-sectional view of a typical Metal Oxide Silicon (MOS) Electrically Erasable Programmable Read Only Memory (EEPROM) cell 19 capable of storing a single binary digit ("bit"). Cell 19 includes P type substrate 10, N type drain 11b, N type source 11a, channel region 13, floating gate 15, control gate 16, tunnel oxide 12 between floating gate 15 and drain extension 11c, dielectric oxide 18 located between floating gate 15 and control gate 16, field oxide 17, and electrical contacts 14a and 14b. Floating gate 15 is capacitively coupled to control gate 16 through dielectric oxide 18.
To program cell 19 to store a logical "one", the drain 11b is connected to a high voltage (typically approximately 21 volts) through contact 14b, and source 11a is either connected to a small positive voltage (approximately 3 volts) through contact 14a or left unconnected ("floating"). Control gate 16 is connected to ground. The ground voltage on control gate 16 is capacitively coupled to floating gate 15, thereby holding floating gate 15 near ground potential. Because of the high positive voltage placed on drain 11b and drain extension 11c, electrons in the floating gate 15 tunnel through the tunnel oxide 12 into the drain extension 11c, thus leaving a net positive charge on floating gate 15. When programming is complete, floating gate 15 retains this positive charge, thus decreasing the voltage required to be placed on control gate 16 to render cell 19 conductive. Thus cell 19, having a decreased control gate threshold voltage (i.e. the voltage on control gate 16 required to turn cell 19 on), stores a logical one. The control gate threshold voltage for a cell 19 which has been programmed to store a logical one is typically zero or slightly negative (e.g. -3 volts). A cell 19 which is not programmed by placing a positive charge on floating gate 15 has a typical control gate threshold voltage of 1 volt.
To erase cell 19, ground voltage is applied to drain 11b via contact 14b and a high positive erase voltage (typically approximately 20 volts) is applied to control gate 16. Electrons then flow from drain extension 11c through tunnel oxide 12 to floating gate 15 thereby discharging floating gate 15 to zero or to a slightly negative voltage. To turn on erased cell 19, a rather high positive voltage on the control gate 16 is needed and the control gate threshold voltage for an "erased" cell 19 is, for example, approximately +5 volts.
To read cell 19, drain 11b is connected to a small positive voltage (typically approximately 2 volts) and source 11a is grounded. A sense amplifier (not shown) detects the current flowing through drain 11b. A read voltage (typically approximately 2 volts) is placed on control gate 16, which is sufficiently positive to turn on cell 19 when cell 19 stores a logical one (i.e. floating gate 15 is charge positive), but which is not sufficiently positive to turn on cell 19 when cell 19 stores a logical zero (i.e. floating gate 15 is charged to zero or slightly negative). The sense amplifier senses the drain current of cell 19, which in turn indicates if cell 19 is turned on or off, which is determined by the logical state (i.e. logical one or zero) of the bit stored in cell 19. Thus, the data stored in cell 19 is read.
An array of EEPROM cells forming an EEPROM device can be made with supporting peripheral circuitry which allows selective programming, erasing and reading. Such an array is described, for example in "A 16Kb Electrically Erasable Nonvolatile Memory" by W. S. Johnson et al., 1980 IEEE International Solid-State Circuits Conference, P. 152, 1980, which is hereby incorporated by reference.
FIG. 1b shows a typical prior art Erasable Programmable Read Only Memory (EPROM) cell 24, containing a control gate 25, floating gate 26, N type source region 28a, N type drain region 28b, dielectric 27, field oxide 29, gate oxide 30, P type channel 32 and P type substrate 31. To program cell 24, high positive voltages (typically approximately 20 volts) are applied to drain 28b and control gate 25, and source 28a is grounded. The high voltage applied to control gate 25 is capacitively coupled to the floating gate 26, which causes channel 32 to conduct, thus turning cell 24 on. Because of the high drain voltage, a rather large quantity of "hot" electrons are generated in the channel 32, such "hot" electrons having sufficiently high energy to overcome the potential barrier of gate oxide 30. These hot electrons are attracted to and collected by the floating gate 26, which is at a positive potential due to the positive voltage applied to control gate 25. These hot electrons which are collected on the floating gate 26 make the floating gate voltage negative and thus raise the control gate threshold voltage of cell 24 by several volts--and a logical "one" bit is stored in cell 24. To read cell 24, read voltages (typically 2 to 3 volts) are supplied to drain 28b and control gate 25, and source 28a is grounded. The read voltage applied to control gate 25 is such that it is not sufficiently high to turn on cell 24 when cell 24 stores a logical one, but is sufficiently high to turn on cell 24 when cell 24 stores a logical zero. A sense amplifier (not shown) is used in a similar fashion as previously described in conjunction with the EEPROM of FIG. 1a, to sense the data stored in cell 24.
To erase EPROM cell 24, UV (ultra-violet) light is used to illuminate the floating gate 26. The passivation oxide 27 surrounding the floating gate 15 is transparent to UV light. UV light has sufficiently high photon energy to impart sufficient energy to the electrons on the floating gate 26 to cause the electrons to overcome the barrier of oxide 30 and leak out from the floating gate 26 to channel 32, thereby discharging floating gate 26.
An array of EPROM cells forming an EPROM device can be made with supporting peripheral circuitry which allows selective programming and reading. Erase is done for the entire array with UV light illumination. Such an array of EPROM cells is described, for example, by G. Perlegos et al., in "A 64K EPROM using Scaled MOS Technology", 1980 IEEE International Solid-State Circuits Conference, Page 142, 1980, which is hereby incorporated by reference.
In integrated circuit capacitors and more particularly in memory devices, a thin dielectric layer between two conductive layers capacitively couples the conductive layers. For example, in Erasable Programmable Read Only Memory (EPROM) memory cells (FIG. 1b) or Electrically Erasable Programmable Read Only Memory (EEPROM) cells (FIG. 1a), a floating gate (for example floating gate 15 of FIG. 1a) is typically separated from the control gate 16 (FIG. 1a) by a thin dielectric layer 18 of silicon dioxide (SiO.sub.2), or silicon nitiride (Si.sub.3 N.sub.4). It is essential that this dielectric layer is very thin in order that the capacitance between the control gate 16 and floating gate 15 is large compared with the capacitance between the floating gate 15 and other regions (e.g., between floating gate 15 and drain extension 11c), thereby causing the voltage on floating gate 15 to closely follow the voltage on control gate 16, thus allowing a large voltage drop across the tunnel oxide 12 to induce tunneling current during programming and erasing. However, the thin layer of dielectric 18 must be of excellent insulative quality so that the charge stored on the floating gate 15 does not leak out over extended periods of time (i.e. 10 yrs at 125.degree. C.), thereby discharging floating gate 15. Providing a dielectric layer which is both very thin and of excellent insulative quality is very difficult. For instance, when the dielectric layer 18 is made excessively thin (i.e. 500 Angstrom or less,) high capacitance between floating gate 15 and control gate 16 is achieved, but the dielectric integrity and insulation properties of dielectric layer 18 are poor. Thus, if a defect exists in dielectric layer 18, control gate 16 may become electrically connected to floating gate 15, thus causing an electrical failure of the device. Alternatively, the poor insulative quality of dielectric 18 allows undesirable charging or discharging of floating gate 15 via control gate 16. In order to prevent such defects in dielectric layer 18, dielectric layer 18 must be formed to a minimum thickness of about 600-700 .ANG. when SiO.sub.2 is used as dielectric 18. The use of this rather thick oxide as dielectric 18 requires a large overlap area between control gate 16 and floating gate 15 in order to achieve the necessary capacitance between floating gate 15 and control gate 16. This large overlap area causes the cell size to be rather large. Large cell size, and thus large device size, is very undersirable in that the product yield rate decreases drastically with an increase in chip size.
Typically, control gate 16 and floating gate 15 are formed for doped polycrystalline silicon (often called "polysilicon" or "poly" for short) because of the well-known advantages of polysilicon gate technology. At leat two problems exist with the use of a "sandwich" formed of polysilicon floating gate 15, SiO.sub.2 dielectric 18, and polysilicon control gate 16. One such problem is the asperities (as shown in FIG. 2) which are rough points at the polysilicon/SiO.sub.2 interfaces between control gate 16 and dielectric 18, and between dielectric 18 and floating gate 15. As shown in FIG. 2, the presence of sharp points C formed by the uneven distribution of silicon atoms along interfaces A and B causes local high electric field at points C and thus dielectric breakdown problems at sharp points C, even with a relatively low voltage difference between control gate 16 and floating gate 15. The low voltage breakdown at point C amy occur at 3 to 4 times lower voltage compared to a layer of SiO.sub.2 of the same thickness but grown on single crystal silicon, rather than on polycrystalline silicon. Another problem present when using the sandwich formed by poly floating gate 15, SiO.sub.2 dielectric 18 and poly control gate 16 is caused by the growth of polysilicon grains after oxide formation. These grains are often large enough to punch through the thin dielectric layer 18 (see FIG. 3), thereby causing an electrical short between control gate 16 and floating gate 15 (FIG. 1a). Silicon grains which do not punch through the dielectric layer 18 reduce the thickness of layer 18, and thus reduce the dielectric strength of dielectric layer 18.
One possible way to achieve high capacitance between control gate 16 and floating gate 15 is to form dielectric 18 from materials with dielectric constants greater than the dielectric constant of SiO.sub.2, such as tantalum oxide or other oxides so that, for a given capacitance, the dielectric layer 18 made from these materials does not need to be as thin as a dielectric layer 18 formed of SiO.sub.2. However, these materials do not have insulation properties as good as silicon dioxide due to poor material composition control and structural instability at high temperatures. Furthermore, the formation of such other oxides are not compatible with current integrated circuit processes and thus such other oxides cannot be easily implemented in nonvolatile integrated circuit memories.
The use of a composite layer of silicon-rich SiO.sub.2 /SiO.sub.2 /silicon-rich SiO.sub.2 between the floating gate and the control gate of a memory device has been described by D. J. DiMaria et al. in an article entitled, "High Current Injection Into SiO.sub.2 Using Si-rich SiO.sub.2 Films and Experimental Applications", The Physics of MOS Insulators, G. Lucovsky, et al. Ed. 1980. The structure described by DiMaria is shown in FIG. 4a. Dielectric layer 44 is formed between polysilicon control gate 46 and polysilicon floating gate 45. Dielectric layer 44 includes three layers 44a, 44b and 44c as shown in more detail in FIG. 4b. Layers 44a and 44c are formed of silicon-rich silicon dioxide (i.e. silicon dioxide including an abundance of excess silicon atoms), and layer 44b is formed of substantially pure silicon dioxide. The operation of the DiMaria EEPROM shown in FIG. 4a is similar to the prior art EEPROM shown in FIG. 1a with one significant difference: floating gate 45 is charged and discharged through control gate 46, and three layer structure 44 is used to inject tunnelling electrons between control gate 46 and floating gate 45 through dielectric 44 to either charge or discharge floating gate 45, as desired. When floating gate 45 is charged positive by causing electrons to tunnel out of the floating gate 45 through dielectric layer 44 into control gate 46, the control gate threshold voltage of DiMaria's transistor 140 is decreased, thus storing a logical one. Conversely, when floating gate 45 is discharged by causing electrons to tunnel from control gate 46 through dielectric 44 into floating gate 45, the control gate threshold voltage of DiMaria's transistor 140 is increased, thus storing a logical zero. As described by DiMaria, by forming a thin SiO.sub.2 layer between two layers of silicon-rich SiO.sub.2, the current injection through the center SiO.sub.2 layer is considerably enhanced as compared with the current injection through a single layer of SiO.sub.2 having a thickness equal to the center SiO.sub.2 layer of the dielectric sandwich. Accordingly, this three layer dielectric structure is sometimes referred to as a "Dual Electron Injector Structure" (DEIS).